Guangyu Zhu, Fei Yuan and Gul Khan
Time-mode circuits where information is represented by the timing difference of digital signals possess a number of intrinsic characteristics that are scaled well with CMOS technology, making them a promising and viable option to implement some of the key building blocks of mixed analog-digital subsystems Analog-to-Digital Converters (ADCs) and Phase-Locked Loops (PLLs). This paper examines the challenges encountered in analog design with technology scaling and presents the fundamental advantages of time-mode circuits. It investigates the building blocks of timemode circuits for mixed analog-digital signal processing with a special focus on ADCs.
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